The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 08, 2023
Filed:
Nov. 29, 2021
Barefoot Networks, Inc., Santa Clara, CA (US);
Jeongkeun Lee, Los Altos, CA (US);
Cole Nathan Schlesinger, Mountain View, CA (US);
John Nathan Foster, Ithaca, NY (US);
Han Wang, San Jose, CA (US);
Robert Soule, Hamden, CT (US);
William Hallahan, Nashua, NH (US);
Steffen Julif Smolka, Ithaca, NY (US);
Mon Jed Liu, Santa Clara, CA (US);
Barefoot Networks, Inc., Santa Clara, CA (US);
Abstract
A method for verifying data plane programs is provided in some embodiments. Because the behavior of a data plane program (e.g., a program written in the P4 language) is determined in part by the control plane populating match-action tables with specific forwarding rules, in some embodiments, programmers are provided with a way to document assumptions about the control plane using annotations (e.g., in the form of 'assertions' or 'assumptions' about the state based on the unknown control plane contribution). In some embodiments, annotations are added automatically to verify common properties, including checking that every header read or written is valid, that every expression has a well-defined value, and that all standard metadata is manipulated correctly. The method in some embodiments translates programs from a first language (e.g., P4) to a second language (e.g., Guarded Command Language (GCL)) for verification by a satisfiability modulo theory (SMT) solver.