The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2023

Filed:

Mar. 28, 2019
Applicant:

Cornell University, Ithaca, NY (US);

Inventors:

Zongyang Hu, Ithaca, NY (US);

Kazuki Nomoto, Ithaca, NY (US);

Grace Huili Xing, Ithaca, NY (US);

Debdeep Jena, Ithaca, NY (US);

Wenshen Li, Ithaca, NY (US);

Assignee:

Cornell University, Ithaca, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); C30B 29/16 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41741 (2013.01); C30B 29/16 (2013.01); H01L 29/66969 (2013.01); H01L 29/7827 (2013.01);
Abstract

A vertical gallium oxide (Ga2O3) device having a substrate, an n-type GaOdrift layer on the substrate, an, n-type semiconducting channel extending from the n-type GaOdrift layer, the channel being one of fin-shaped or nanowire shaped, an n-type source layer disposed on the channel; the source layer has a higher doping concentration than the channel, a first dielectric layer on the n-type Ga2O3 drift layer and on sidewalls of the n-type semiconducting channel, a conductive gate layer deposited on the first dielectric layer and insulated from the n-type source layer, n-type semiconducting channel as well as n-type Ga2O3 drift layer, a second dielectric layer deposited over the conductive gate layer, covering completely the conductive gate layer on channel sidewalls and an ohmic source contact deposited over the n-type source layer and over at least a part of the second dielectric layer; the source contact being configured not to be in electrical contact with the conductive gate layer.


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