The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2023

Filed:

Jan. 13, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Dong-Hyun Im, Suwon-si, KR;

Kibum Lee, Suwon-si, KR;

Daehyun Kim, Suwon-si, KR;

Ju Hyung We, Hwaseong-si, KR;

Sungmi Yoon, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 21/763 (2006.01); H01L 21/02 (2006.01); H01L 27/146 (2006.01); H01L 29/78 (2006.01); H01L 21/8238 (2006.01); H01L 21/8234 (2006.01); H10B 12/00 (2023.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
H01L 21/76224 (2013.01); H01L 21/02238 (2013.01); H01L 21/02667 (2013.01); H01L 21/763 (2013.01); H01L 21/8238 (2013.01); H01L 21/823481 (2013.01); H01L 21/823878 (2013.01); H01L 27/1463 (2013.01); H01L 29/785 (2013.01); H10B 12/053 (2023.02); H10B 12/482 (2023.02); H10B 41/27 (2023.02); H10B 43/27 (2023.02); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01);
Abstract

A semiconductor device and a method of fabricating a semiconductor device, the device including a semiconductor substrate that includes a trench defining an active region; a buried dielectric pattern in the trench; a silicon oxide layer between the buried dielectric pattern and an inner wall of the trench; and a polycrystalline silicon layer between the silicon oxide layer and the inner wall of the trench, wherein the polycrystalline silicon layer has a first surface in contact with the semiconductor substrate and a second surface in contact with the silicon oxide layer, and wherein the second surface includes a plurality of silicon grains that are uniformly distributed.


Find Patent Forward Citations

Loading…