The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 2023
Filed:
Aug. 10, 2022
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Chien-Hao Huang, Hsinchu, TW;
Katherine H. Chiang, Hsinchu, TW;
Cheng-Yi Wu, Hsinchu, TW;
Chung-Te Lin, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A method of testing a non-volatile memory (NVM) array includes obtaining a current distribution of a subset of NVM cells of the NVM array, the current distribution including first and second portions corresponding to respective logically high and low states of the subset of NVM cells, programming an entirety of the NVM cells of the NVM array to one of the logically high or low states, determining an initial bit error rate (BER) by performing first and second pass/fail (P/F) tests on each NVM cell of the NVM array, and using the current distribution to adjust the initial BER rate. Each of obtaining the current distribution, programming the entirety of the NVM cells, and performing the first and second P/F tests is performed while the NVM array is heated to a target temperature.