The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2023

Filed:

Jun. 25, 2021
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

Russell J. Schreiber, Austin, TX (US);

John J. Wuu, Ft. Collins, CO (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); G11C 11/4096 (2006.01); G11C 11/408 (2006.01); G11C 7/10 (2006.01); G11C 11/4074 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4096 (2013.01); G11C 7/106 (2013.01); G11C 7/1009 (2013.01); G11C 7/1087 (2013.01); G11C 11/4074 (2013.01); G11C 11/4085 (2013.01); G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/3404 (2013.01);
Abstract

A bit cell of an SRAM implemented using standard cell design rules includes a write portion and a read portion. The write portion includes a pass gate coupled to an input node of the bit cell and supplies data on the input node to a first node of the bit cell while write word line signals are asserted. An inverter is coupled to the first node and supplies inverted data. A keeper circuit that is coupled to the inverter maintains the data on the first node when the write word line signals are deasserted. The read portion of the bit cell receives read word line signals and the inverted data and is responsive to assertion of the read word line signals to supply an output node of the read portion of the bit cell with output data that corresponds to the data on the first node.


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