The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 2023
Filed:
May. 07, 2021
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Cheng-Hua Liu, Hsinchu County, TW;
Yun-Xiang Lin, Hsinchu County, TW;
Yuan-Te Hou, Hsinchu, TW;
Chung-Hsing Wang, Hsinchu County, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/00 (2020.01); G06F 30/398 (2020.01); G06F 30/367 (2020.01); G06F 30/20 (2020.01); G06F 30/39 (2020.01); G06F 119/10 (2020.01); G06F 30/392 (2020.01); G06F 119/18 (2020.01); G06F 111/20 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/20 (2020.01); G06F 30/367 (2020.01); G06F 30/39 (2020.01); G06F 30/392 (2020.01); G06F 2111/20 (2020.01); G06F 2119/10 (2020.01); G06F 2119/18 (2020.01);
Abstract
A method includes: identifying attributes that are associated with cell edges of abutted cells in a layout of a semiconductor device, wherein the attributes include at least one of terminal types of the cell edges; determining at least one minimal boundary leakage of the abutted cells based on the attributes, for adjustment of the layout of the semiconductor device. A system is also disclosed herein.