The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2023

Filed:

Nov. 22, 2021
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Jeffrey Ellis Byrd, Greensboro, NC (US);

Peter C. de Jong, Oosterbeek, NL;

Herman Luijmes, Didam, NL;

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 1/06 (2006.01); G01R 31/00 (2006.01); G01R 27/18 (2006.01); G01R 1/067 (2006.01); G01R 19/155 (2006.01); G01N 27/07 (2006.01); G01N 27/02 (2006.01); G01N 15/06 (2006.01);
U.S. Cl.
CPC ...
G01R 31/002 (2013.01); G01R 1/06722 (2013.01); G01R 1/06788 (2013.01); G01R 19/155 (2013.01); G01R 27/18 (2013.01); G01N 15/0656 (2013.01); G01N 27/02 (2013.01); G01N 27/07 (2013.01);
Abstract

Some aspects of this disclosure are directed to an automated method to check electrostatic discharge (ESD) effect on a victim device. For example, some aspects of this disclosure relate to a method, including determining a probe point, in a circuit design, for determining effective resistance between the probe point and ground, where the probe point is on an ESD path of in the circuit design. The method includes determining voltage between the probe point and the ground. The method further includes comparing, by a processing device, a resistance value of the ESD path determined based a predefined electric current value at a source point and the measured voltage with a target resistance value range. The method further includes reporting a violation upon determining that the determined resistance value of the ESD path is outside the target resistance value range.


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