The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2023

Filed:

Aug. 02, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsin-Chu, TW;

Inventors:

Chih-Ming Chen, Hsinchu, TW;

Yuan-Chih Hsieh, Hsinchu, TW;

Chung-Yi Yu, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B81B 7/00 (2006.01); B81C 1/00 (2006.01); H01L 23/488 (2006.01); H01L 25/00 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
B81C 1/00269 (2013.01); B81B 7/0041 (2013.01); B81C 1/00 (2013.01); B81C 1/00238 (2013.01); H01L 23/488 (2013.01); H01L 25/50 (2013.01); B81B 2201/0235 (2013.01); B81B 2201/0242 (2013.01); B81B 2201/0264 (2013.01); B81B 2207/012 (2013.01); B81B 2207/093 (2013.01); B81C 2201/019 (2013.01); B81C 2201/0132 (2013.01); B81C 2203/0118 (2013.01); B81C 2203/035 (2013.01); B81C 2203/036 (2013.01); H01L 24/02 (2013.01); H01L 24/06 (2013.01); H01L 24/81 (2013.01);
Abstract

The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.


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