The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 25, 2023

Filed:

Apr. 12, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Kyung Hwan Lee, Hwaseong-si, KR;

Yong Seok Kim, Suwon-si, KR;

Hyun Cheol Kim, Seoul, KR;

Satoru Yamada, Yongin-si, KR;

Sung Won Yoo, Hwaseong-si, KR;

Jae Ho Hong, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/70 (2023.01); H10B 41/20 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 41/50 (2023.01);
U.S. Cl.
CPC ...
H10B 41/70 (2023.02); H10B 41/20 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 41/50 (2023.02);
Abstract

Provided is a semiconductor memory device. The semiconductor memory device comprises a first semiconductor pattern including a first impurity region, a second impurity region, and a channel region, the first impurity region spaced apart from a substrate in a first direction and having a first conductivity type, the second impurity region having a second conductivity type different from the first conductivity type, and the channel region between the first impurity region and the second impurity region, a first conductive connection line connected to the first impurity region and extending in a second direction different from the first direction and a first gate structure extending in the first direction and including a first gate electrode and a first gate insulating film, wherein the first gate electrode penetrates the channel region and the first gate insulating film is between the first gate electrode and the semiconductor pattern.


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