The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 25, 2023

Filed:

Jul. 30, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Po-Zeng Kang, Hsinchu, TW;

Wen-Shen Chou, Hsinchu, TW;

Yung-Chow Peng, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/158 (2006.01); H03K 17/22 (2006.01); H03K 19/0185 (2006.01); H03K 17/687 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
H03K 17/6872 (2013.01); H03K 19/20 (2013.01);
Abstract

A semiconductor device includes a hysteresis block configured to generate an output voltage at corresponding disabling enabling voltage levels and a core-voltage-gated (CVG) device configured to receive a core voltage, an input terminal of the hysteresis block is coupled to a control node. The CVG device is configured to alter a control voltage at the control node so as to cause the output voltage of the hysteresis block to be generated at the disabling voltage level in response to the core voltage being at or below a first trigger level. Additionally, the CVG device is configured to alter the control voltage at the control node so as to cause the output voltage of the hysteresis block to be generated at the enabling voltage level in response to the core voltage being at or above a second trigger level, the second trigger level being above the first trigger level.


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