The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 25, 2023
Filed:
May. 29, 2022
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Po-Lin Peng, Taoyuan, TW;
Yu-Ti Su, Tainan, TW;
Chia-Wei Hsu, New Taipei, TW;
Ming-Fu Tsai, Hsinchu, TW;
Shu-Yu Su, Hsinchu, TW;
Li-Wei Chu, Hsinchu, TW;
Jam-Wem Lee, Hsinchu, TW;
Chia-Jung Chang, Hsinchu, TW;
Hsiang-Hui Cheng, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Abstract
A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. A first terminal of the first transistor is configured to receive a reference voltage signal, a control terminal of the first transistor is configured to receive a detection signal in response to an ESD event being detected, a second terminal of the first transistor is coupled to a control terminal of the third transistor, and a control terminal of the second transistor is configured to receive the logic control signal.