The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 25, 2023

Filed:

Feb. 17, 2021
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Je Hyun Choi, Icheon-si, KR;

Sung Lae Oh, Icheon-si, KR;

Soo Yeol Chai, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); H01L 25/18 (2023.01); H01L 23/00 (2006.01); G11C 16/30 (2006.01); G11C 16/24 (2006.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); G11C 7/10 (2006.01); G11C 16/08 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); G11C 16/0483 (2013.01); G11C 16/24 (2013.01); G11C 16/30 (2013.01); H01L 24/05 (2013.01); H01L 24/20 (2013.01); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); G11C 7/1039 (2013.01); G11C 16/08 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1438 (2013.01);
Abstract

A memory device includes a cell wafer having a first pad on one surface thereof; and a peripheral wafer bonded to the one surface of the cell wafer, and having a second pad coupled to the first pad. The cell wafer includes a memory cell array; first and second bit lines coupled to the memory cell array; and a bit line selection circuit configured to couple one of the first and second bit lines to the first pad. The peripheral wafer includes a page buffer low-voltage circuit including a first page buffer low-voltage unit corresponding to the first bit line and a second page buffer low-voltage unit corresponding to the second bit line; and a page buffer high-voltage circuit configured to couple one of the first and second page buffer low-voltage units to the second pad.


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