The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 25, 2023
Filed:
May. 24, 2019
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Ebubekir Dogan, Portland, OR (US);
Ramanan Ehamparam, Beaverton, OR (US);
Jiho Kang, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 25/18 (2023.01); H01L 25/16 (2023.01); H01L 23/522 (2006.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 23/3128 (2013.01); H01L 23/5283 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 25/0655 (2013.01); H01L 2224/0401 (2013.01);
Abstract
Integrated circuit (IC) structures include transistor devices with interconnect structures, e.g., a source contact, drain contact, and/or gate contact. The interconnect structures have rounded top surfaces. Contouring the top surfaces of transistor contacts may decrease the likelihood of electrical shorting and may permit a larger volume of insulating dielectric between adjacent contacts.
Dogan, Ebubekir. (2023). Integrated circuit structures with contoured interconnects (U.S. Patent No. 11710694). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11710694
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile