The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 25, 2023

Filed:

Feb. 28, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Christian N. Mohr, Allen, TX (US);

Scott E. Smith, Plano, TX (US);

Manoj Vijay, Dallas, TX (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/52 (2006.01); G11C 29/02 (2006.01); G11C 29/46 (2006.01); G11C 29/00 (2006.01); G11C 29/12 (2006.01); G11C 29/38 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 29/52 (2013.01); G11C 29/021 (2013.01); G11C 29/12005 (2013.01); G11C 29/38 (2013.01); G11C 29/46 (2013.01); G11C 29/787 (2013.01); G11C 2029/0409 (2013.01);
Abstract

Embodiments presented herein are directed to testing and/or debugging a memory device of a memory module (e.g., a dual in-line memory module (DIMM)) without having to remove the DIMM from a corresponding computing device and without having to interrupt operation of the computing device. A particular memory device (e.g., DRAM) may be identified for testing and/or debugging based on a failure message. However, the failure message may not identify a specific location or hardware of the module that caused the failure. Embodiments presented herein provide techniques to obtain data for analysis to determine and/or deliver a cause of the failure while reducing or eliminating downtime of the computing device. Test modes to do so may include a synchronous test mode, an asynchronous test mode, and an analog compare mode. A test mode may be selected based on the failure or a signal/function of the DRAM to be tested or debugged.


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