The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 25, 2023

Filed:

Jan. 14, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Koji Sakui, Tokyo, JP;

Mark Hawes, Boise, ID (US);

Toru Tanzawa, Tokyo, JP;

Jeremy Binfet, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/26 (2006.01); G11C 7/04 (2006.01); G11C 16/30 (2006.01); G11C 16/34 (2006.01); G11C 16/20 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 69/00 (2023.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/14 (2006.01); G11C 16/32 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 7/04 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/14 (2013.01); G11C 16/20 (2013.01); G11C 16/30 (2013.01); G11C 16/32 (2013.01); G11C 16/3418 (2013.01); G11C 16/3427 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 69/00 (2023.02);
Abstract

Apparatus might include an array of memory cells and a controller to perform access operations on the array of memory cells. The controller might be configured to establish a negative potential in a body of a memory cell of the array of memory cells, and initiate a sensing operation on the memory cell while the body of the memory cell has the negative potential. Apparatus might further include an array of memory cells, a timer, and a controller to perform access operations on the array of memory cells. The controller might be configured to advance the timer, and establish a negative potential in a body of a memory cell of the array of memory cells in response to a value of the timer having a desired value.


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