The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 18, 2023
Filed:
Jun. 16, 2021
Synopsys, Inc., Mountain View, CA (US);
Ashima Sahil Dabare, Noida, IN;
Sanjiv Mathur, Noida, IN;
Anusha Reddy Sindhwala, Bangalore, IN;
Prakasha Karkada Holla, Bangalore, IN;
Sivakumar Arulanantham, Hillsboro, OR (US);
Srinivasan Krishnamurthy, Hillsboro, OR (US);
Chun-Cheng Chi, Mountain View, CA (US);
Shih-Pin Hung, Hsinchu, TW;
Synopsys, Inc., Sunnyvale, CA (US);
Abstract
Embodiments provide for building a global clock tree. In embodiments, an example method includes inserting clock drivers at symmetric locations in one or more hierarchy levels of a plurality of hierarchy levels of an integrated circuit (IC) design. The example method further includes generating one or more routes by routing one or more nets within or across the one or more hierarchy levels of the plurality of hierarchy levels. The example method further includes matching symmetric routes of the one or more routes at each of the one or more hierarchy levels irrespective of a number of physical hierarchies each associated net spans. The example method further includes placing one or more ports at one or more signal entry points where routes of the one or more routes cross physical hierarchy blocks.