The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2023

Filed:

Jul. 19, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Michael E. Kounavis, Portland, OR (US);

Santosh Ghosh, Hillsboro, OR (US);

Sergej Deutsch, Hillsboro, OR (US);

Michael LeMay, Hillsboro, OR (US);

David M. Durham, Beaverton, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 16/22 (2019.01); G06F 16/2457 (2019.01); G06F 16/2455 (2019.01); G06F 9/38 (2018.01); G06F 21/60 (2013.01); G06F 21/62 (2013.01); H03M 13/00 (2006.01);
U.S. Cl.
CPC ...
G06F 16/2255 (2019.01); G06F 9/3885 (2013.01); G06F 16/24552 (2019.01); G06F 16/24573 (2019.01); G06F 21/602 (2013.01); G06F 21/6218 (2013.01); H03M 13/6516 (2013.01);
Abstract

Embodiments are directed to collision-free hashing for accessing cryptographic computing metadata and for cache expansion. An embodiment of an apparatus includes one or more processors to: receive a physical address; compute a set of hash functions using a set of different indexes corresponding to the set of hash functions, wherein the set of hash functions combine additions, bit-level reordering, bit-linear mixing, and wide substitutions, wherein the plurality of hash functions differ in the bit-linear mixing; access a plurality of cache units utilizing the set of hash functions; read different sets of the plurality of cache units in parallel, where a set of the different sets is obtained from each cache unit of the plurality of cache units; and responsive to the physical address being located one of the different sets, return cache line data of the set corresponding to the set of the cache unit having the physical address.


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