The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2023

Filed:

Dec. 26, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Robert Southworth, Chatsworth, CA (US);

Karl S. Papadantonakis, Agoura Hills, CA (US);

Mika Nystroem, Pasadena, CA (US);

Arvind Srinivasan, San Jose, CA (US);

David Arditti Ilitzky, Zapopan, MX;

Jonathan Dama, Encino, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 47/625 (2022.01); H04L 49/901 (2022.01); H04L 67/568 (2022.01);
U.S. Cl.
CPC ...
H04L 47/6255 (2013.01); H04L 49/901 (2013.01); H04L 67/568 (2022.05);
Abstract

Examples describe use of multiple meta-data delivery schemes to provide tags that describe packets to an egress port group. A tag, that is smaller than a packet, can be associated with a packet. The tag can be stored in a memory, as a group with other tags, and the tag can be delivered to a queue associated with an egress port. Packets received at an ingress port can be as non-interleaved to reduce underrun and providing cut-through to an egress port. A shared memory can be allocated to store packets received at a single ingress port or shared to store packets from multiple ingress ports.


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