The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2023

Filed:

Jul. 11, 2019
Applicants:

Namlab Ggmbh, Dresden, DE;

Technische Universität Dresden, Dresden, DE;

Inventors:

Stefan Schmult, Dresden, DE;

Andre Wachowiak, Dresden, DE;

Alexander Ruf, Dresden, DE;

Assignees:

NAMLAB GGMBH, Dresden, DE;

TECHNISCHE UNIVERSITÄT DRESDEN, Dresden, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/78 (2006.01); H01L 29/778 (2006.01); H01L 29/20 (2006.01); H01L 29/22 (2006.01); H01L 29/225 (2006.01); H01L 29/205 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7787 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/22 (2013.01); H01L 29/225 (2013.01); H01L 29/7788 (2013.01);
Abstract

An electronic circuit having a semiconductor device is provided that includes a heterostructure, the heterostructure including a first layer of a compound semiconductor to which a second layer of a compound semiconductor adjoins in order to form a channel for a 2-dimensional electron gas (2DEG), wherein the 2-dimensional electron gas is not present. In aspects, an electronic circuit having a semiconductor device is provided that includes a III-V heterostructure, the III-V heterostructure including a first layer including GaN to which a second layer adjoins in order to form a channel for a 2-dimensional electron gas (2DEG), and having a purity such that the 2-dimensional electron gas is not present. It is therefore advantageous for the present electronic circuit to be enclosed such that, in operation, no light of wavelengths of less than 400 nm may reach the III-V heterostructure and free charge carriers may be generated by these wavelengths.


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