The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 11, 2023
Filed:
Nov. 18, 2021
Renesas Electronics Corporation, Tokyo, JP;
Keita Tsuchiya, Tokyo, JP;
Shuuichi Kariyazaki, Tokyo, JP;
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Abstract
A semiconductor device includes a wiring substrate having: a first wiring layer having pads; and a second wiring layer having wirings and via-lands. The via-lands include: first-row via-lands connected to first-row pads of the pads, respectively; and second-row via-lands connected to the second-row pads of the pads, respectively. In the perspective plan view, the first-row via-lands have: first via-lands arranged such that a center of each of the first via-lands is shifted in a direction away from a first side of the semiconductor chip than a position overlapping with a center of the corresponding first-row pad; and second via-lands arranged such that a center of each of the second via-lands arranged at a position closer to the first side than the first via-land. In the perspective plan view, the first and second via-lands are alternately arranged in a first direction along the first side.