The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2023

Filed:

Mar. 18, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventor:

Tien-Chien Huang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/20 (2020.01); G06F 111/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/20 (2020.01); G06F 2111/12 (2020.01);
Abstract

A method of generating a layout diagram of an IC device includes assigning a leakage constraint to a first schematic net of the IC device and determining a violation of the leakage constraint based on a dummy gate region. The IC layout diagram includes the dummy gate region between a first component of the first schematic net and a second component of a second schematic net of the IC device. The method includes modifying the IC layout diagram in response to the leakage constraint violation, and generating a layout file based on the modified IC layout diagrams.


Find Patent Forward Citations

Huang, Tien-Chien. (2023). Integrated circuit design method and system (U.S. Patent No. 11699009). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11699009

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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