The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2023

Filed:

Oct. 07, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Stephen Glancy, Yorktown, VA (US);

Kyu-hyoun Kim, Chappaqua, NY (US);

Warren E. Maule, Cedar Park, TX (US);

Kevin M. Mcilvain, Delmar, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/16 (2006.01); G11C 29/42 (2006.01); G11C 29/00 (2006.01); G06F 11/10 (2006.01); G11C 29/44 (2006.01); G11C 29/52 (2006.01); G11C 29/12 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1666 (2013.01); G06F 11/1068 (2013.01); G11C 29/42 (2013.01); G11C 29/44 (2013.01); G11C 29/52 (2013.01); G11C 29/70 (2013.01); G11C 29/76 (2013.01); G11C 2029/1204 (2013.01);
Abstract

A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.


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