The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 04, 2023
Filed:
Feb. 25, 2021
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Wei Hu, San Diego, CA (US);
Dongming He, San Diego, CA (US);
Wen Yin, Chandler, AZ (US);
Zhe Guan, Chandler, AZ (US);
Lily Zhao, San Diego, CA (US);
Assignee:
QUALCOMM INCORPORATED, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/13 (2013.01); H01L 24/05 (2013.01); H01L 24/11 (2013.01); H01L 2224/11013 (2013.01); H01L 2224/11622 (2013.01); H01L 2224/11849 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13584 (2013.01); H01L 2224/13655 (2013.01);
Abstract
Disclosed are examples of integrated circuit (IC) structures and techniques to fabricate IC structures. Each IC package may include a die (e.g., a flip-chip (FC) die) and one or more die interconnects to electrically couple the die to a substrate. The die interconnect may include a pillar, a wetting barrier on the pillar, and a solder cap on the wetting barrier. The wetting barrier may be wider than the pillar. The die interconnect may also include a low wetting layer formed on the wetting barrier.