The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2023

Filed:

Sep. 20, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Jeremiah J. Willcock, Boise, ID (US);

Richard C. Murphy, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0871 (2016.01); G06F 12/0873 (2016.01); G06F 12/02 (2006.01); G11C 11/403 (2006.01); G11C 11/4091 (2006.01); G11C 11/4093 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01); G11C 7/10 (2006.01); G11C 7/06 (2006.01); G06F 12/0893 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0871 (2013.01); G06F 12/0215 (2013.01); G06F 12/0873 (2013.01); G11C 7/1006 (2013.01); G11C 11/403 (2013.01); G11C 11/4091 (2013.01); G11C 11/4093 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01); G06F 12/0893 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1028 (2013.01); G11C 7/065 (2013.01); G11C 2207/002 (2013.01); G11C 2207/005 (2013.01); G11C 2211/4013 (2013.01); Y02D 10/00 (2018.01);
Abstract

The present disclosure includes apparatuses and methods for cache operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes sensing circuitry coupled to the first subset, the sensing circuitry including a sense amplifier and a compute component. The first subset is configured as a cache to perform operations on data moved from the second subset. The apparatus also includes a cache controller configured to direct a first movement of a data value from a subarray in the second subset to a subarray in the first subset.


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