The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2023

Filed:

May. 31, 2021
Applicant:

Redpine Signals, Inc., San Jose, CA (US);

Inventors:

Martin Kraemer, Mountain View, CA (US);

Ryan Boesch, Louisville, CO (US);

Wei Xiong, Mountain View, CA (US);

Assignee:

Ceremorphic, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06J 1/00 (2006.01); G06F 7/544 (2006.01); G06G 7/16 (2006.01); H03K 19/20 (2006.01); H03M 1/38 (2006.01); H03M 3/04 (2006.01);
U.S. Cl.
CPC ...
G06J 1/00 (2013.01); G06F 7/5443 (2013.01); G06G 7/16 (2013.01); G06F 2207/3864 (2013.01); H03K 19/20 (2013.01); H03M 1/38 (2013.01); H03M 3/04 (2013.01);
Abstract

A Bias Unit Element (UE) has a digital input, a sign input, and a chop clock. The sign input is exclusive ORed with the chop clock to generate a signed chop clock. Each Bias UE comprises a positive Bias UE and a negative Bias UE, each comprising groups of NAND gates generating an output and a complementary output, each of which are coupled to differential charge transfer lines through binary weighted charge transfer capacitors to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The chopped sign input enables the positive Bias UE when the sign bit is positive and enables the negative Bias UE when the sign bit is negative.


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