The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2023

Filed:

Apr. 20, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ned Smith, Beaverton, OR (US);

Changzheng Wei, Shanghai, CN;

Songwu Shen, Shanghai, CN;

Ziye Yang, Shanghai, CN;

Junyuan Wang, Shanghai, CN;

Weigang Li, Shanghai, CN;

Wenqian Yu, Shanghai, CN;

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 21/76 (2013.01); G06F 21/60 (2013.01);
U.S. Cl.
CPC ...
G06F 9/5044 (2013.01); G06F 9/505 (2013.01); G06F 21/76 (2013.01); G06F 21/602 (2013.01); G06F 2209/509 (2013.01); Y02D 10/00 (2018.01);
Abstract

Technologies for hybrid field-programmable gate array (FPGA) application-specific integrated circuit (ASIC) code acceleration are described. In one example, the computing device includes a FPGA comprising: algorithm circuitry to: perform one or more algorithm tasks of an algorithm, wherein the algorithm to perform a service request that is offloaded to the FPGA; and determine a primitive task associated with an algorithm task of the one or more algorithm tasks; primitive offload circuitry to encapsulate the primitive task in a buffer of the FPGA, wherein the buffer is accessible by an ASIC of the computing device; and result circuitry to return one or more results of the service request responsive to performance of the primitive task by the ASIC.


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