The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 20, 2023
Filed:
Aug. 16, 2021
Applicant:
Nanya Technology Corporation, New Taipei, TW;
Inventors:
Assignee:
NANYA TECHNOLOGY CORPORATION, New Taipei, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H10B 12/00 (2023.01); H01F 10/32 (2006.01); H01L 23/58 (2006.01); H01L 29/49 (2006.01); H01L 21/28 (2006.01); H01L 29/40 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); G11C 11/16 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01);
U.S. Cl.
CPC ...
H10B 12/50 (2023.02); G11C 11/161 (2013.01); H01F 10/329 (2013.01); H01F 10/3254 (2013.01); H01L 21/28035 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/585 (2013.01); H01L 29/401 (2013.01); H01L 29/4916 (2013.01); H10B 12/053 (2023.02); H10B 12/315 (2023.02); H10B 12/34 (2023.02); H10B 12/482 (2023.02); H10B 61/22 (2023.02); H10N 50/01 (2023.02); H10N 50/80 (2023.02);
Abstract
The present disclosure provides a method of fabricating a semiconductor device. The method includes: providing a semiconductor substrate comprising a memory region and a logic region; forming a memory gate in or on the memory region; forming a plurality of first poly-silicon gates on the memory region and surrounding the memory gate; and forming a plurality of second poly-silicon gates on the logic region simultaneously with the formation of the first poly-silicon gates.