The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2023

Filed:

Oct. 21, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chih-I Peng, Hsinchu, TW;

Hsiu-Ming Yeh, Hsinchu, TW;

Yi-Chang Liu, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/677 (2006.01); H01L 21/67 (2006.01); H01L 21/306 (2006.01); B24B 37/10 (2012.01);
U.S. Cl.
CPC ...
H01L 21/02057 (2013.01); B24B 37/10 (2013.01); H01L 21/02074 (2013.01); H01L 21/30625 (2013.01); H01L 21/67051 (2013.01); H01L 21/67173 (2013.01); H01L 21/67219 (2013.01); H01L 21/67748 (2013.01); H01L 21/67259 (2013.01);
Abstract

A system for performing a chemical mechanical polishing (CMP) process is provided. The system includes a CMP tool configured to polish a semiconductor wafer. The processing system further includes a wafer stage configured to support the semiconductor wafer for facilitating the insertion of the semiconductor wafer into, and its subsequent removal from, the CMP tool. The processing system also includes a number of spray nozzles positioned relative to the wafer stage. In addition, the processing system includes a spray generator connected to the spray nozzles and configured to convert a mixture to a mist spray. The processing system further includes a controller configured to activate flow of the mist spray from the spray generator to the spray nozzles to discharge the mist spray over the semiconductor wafer supported by the wafer stage.


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