The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2023

Filed:

Feb. 07, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yao-Wen Hsu, New Taipei, TW;

Ching-Hung Kao, Tainan, TW;

Po-Jen Wang, Taichung, TW;

Tsung-Han Tsai, Miaoli County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/683 (2006.01); H01L 21/687 (2006.01); H01L 21/67 (2006.01); H01L 21/22 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02016 (2013.01); H01L 21/02002 (2013.01); H01L 21/22 (2013.01); H01L 21/67103 (2013.01); H01L 21/6831 (2013.01); H01L 21/68757 (2013.01); H01L 21/68764 (2013.01); H01L 21/68785 (2013.01); H01J 2237/31701 (2013.01); H01L 27/1203 (2013.01);
Abstract

A method comprises depositing a mask layer on a front-side surface of a wafer, wherein a portion of the wafer has a first resistivity; with the mask layer in place, performing an ion implantation process on a backside surface of the wafer to implant a resistivity reduction impurity into the wafer through the backside surface of the wafer to lower the first resistivity of the portion of the wafer to a second resistivity; after performing the ion implantation process, removing the mask layer from the front-side surface of the wafer; and forming semiconductor devices on the front-side surface of the wafer.


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