Direct cache hit and transfer in a memory sub-system that programs sequentially

Abstract

A system includes a memory device; a volatile memory comprising buffers; and a processing device to perform operations comprising: accessing a read command having a first command tag, the first command tag comprising a first logical transfer unit (LTU) value and a first buffer address for a first buffer, the first LTU value being mapped from a zone of a plurality of sequential logical block address (LBA) values to a first physical address, of the memory device, at which is stored first data; and generating a set of command tags that are to cause second data to be retrieved from the memory device and stored in a set of the buffers, wherein the set of command tags comprises at least a second command tag associated with a second physical address that sequentially follows the first physical address.