The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2023

Filed:

Aug. 24, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Swagath Venkataramani, Tirupur, IN;

Dipankar Das, Pune, IN;

Sasikanth Avancha, Bangalore, IN;

Ashish Ranjan, West Lafayette, IN (US);

Subarno Banerjee, Kolkata, IN;

Bharat Kaul, Bengaluru, IN;

Anand Raghunathan, West Lafayette, IN (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/14 (2006.01); G06F 9/30 (2018.01); G06N 3/04 (2023.01); G06N 3/084 (2023.01); G06N 3/063 (2023.01); G06F 9/52 (2006.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 9/30145 (2013.01); G06F 9/3004 (2013.01); G06F 9/30043 (2013.01); G06F 9/30087 (2013.01); G06F 9/3834 (2013.01); G06F 9/52 (2013.01); G06N 3/04 (2013.01); G06N 3/063 (2013.01); G06N 3/084 (2013.01);
Abstract

Systems, methods, and apparatuses relating to access synchronization in a shared memory are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, and an execution unit to execute the decoded instruction to: receive a first input operand of a memory address to be tracked and a second input operand of an allowed sequence of memory accesses to the memory address, and cause a block of a memory access that violates the allowed sequence of memory accesses to the memory address. In one embodiment, a circuit separate from the execution unit compares a memory address for a memory access request to one or more memory addresses in a tracking table, and blocks a memory access for the memory access request when a type of access violates a corresponding allowed sequence of memory accesses to the memory address for the memory access request.


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