The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2023

Filed:

Mar. 08, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Jason T. Zawodny, Grand Rapids, MI (US);

Glen E. Hush, Boise, ID (US);

Troy A. Manning, Meridian, ID (US);

Timothy P. Finkbeiner, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 7/10 (2006.01); G11C 8/12 (2006.01); G06F 15/78 (2006.01); G11C 29/28 (2006.01); G11C 29/26 (2006.01); G11C 5/02 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0611 (2013.01); G06F 3/0625 (2013.01); G06F 3/0659 (2013.01); G06F 3/0683 (2013.01); G06F 15/7821 (2013.01); G11C 7/10 (2013.01); G11C 7/1006 (2013.01); G11C 8/12 (2013.01); G11C 29/28 (2013.01); G11C 5/025 (2013.01); G11C 2029/2602 (2013.01);
Abstract

The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.


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