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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11681342 B1

PDFFull Text
Date of Patent:
Jun. 20, 2023

Filed:

Jan. 04, 2021

Memory controller with processor for generating interface adjustment signals

Applicant:

Rambus Inc., San Jose, CA (US);

Inventor:

Stephen G. Tell, Chapel Hill, NC (US);

Assignee:

RAMBUS INC., San Jose, CA (US);

Attorney:

Morgan, Lewis & Bockius LLP

Primary Examiner:

Yong J Choe

Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 1/26 (2006.01); G06F 13/40 (2006.01); H04L 7/02 (2006.01); G06F 1/10 (2006.01); G06F 13/38 (2006.01); G06F 12/02 (2006.01); G11C 7/10 (2006.01); H03K 19/1776 (2020.01);
U.S. Cl.
CPC ...
G06F 1/26 (2013.01); G06F 1/10 (2013.01); G06F 12/0246 (2013.01); G06F 13/382 (2013.01); G06F 13/4072 (2013.01); G11C 7/1072 (2013.01); H03K 19/1776 (2013.01); H04L 7/02 (2013.01); G06F 2212/7201 (2013.01);
Abstract

A circuit interface includes one or more processors that generate opcodes, a plurality of interface control circuits, each including a respective processing element responsive to the opcodes generated by one or more processors. Each interface control circuit corresponds to a respective link of a plurality of links of a device-to-device interface (DDI), and each link of the plurality of links of the DDI is for transmitting or receiving signals from one or more sources or one or more destinations external to the circuit.

Find Patent Forward Citations

Tell, Stephen. (2023). Memory controller with processor for generating interface adjustment signals (U.S. Patent No. 11681342). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11681342

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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