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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11678491 B1

PDFFull Text
Date of Patent:
Jun. 13, 2023

Filed:

Jun. 02, 2021

Embedded memory using soi structures and methods

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chien Hung Liu, Hsinchu County, TW;

Chih-Wei Hung, Hsinchu, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Attorney:

Eschweiler & Potashnik, LLC

Primary Examiner:

Syed I Gheyas

Int. Cl.
CPC ...
H10B 43/30 (2023.01); H01L 27/11568 (2017.01); G11C 16/24 (2006.01); H01L 27/11573 (2017.01); H01L 29/08 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 21/84 (2006.01); H01L 21/3213 (2006.01); H01L 21/321 (2006.01); H01L 21/265 (2006.01); H01L 21/02 (2006.01); H01L 21/324 (2006.01); H01L 21/762 (2006.01); G11C 16/08 (2006.01); G11C 16/22 (2006.01); H01L 29/792 (2006.01); H01L 27/12 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); G11C 16/08 (2013.01); G11C 16/22 (2013.01); G11C 16/24 (2013.01); H01L 21/02636 (2013.01); H01L 21/26513 (2013.01); H01L 21/324 (2013.01); H01L 21/3212 (2013.01); H01L 21/32133 (2013.01); H01L 21/76283 (2013.01); H01L 21/84 (2013.01); H01L 27/11573 (2013.01); H01L 27/1203 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/40117 (2019.08); H01L 29/42328 (2013.01); H01L 29/42364 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/6659 (2013.01); H01L 29/66545 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01); G11C 16/0466 (2013.01); H01L 29/665 (2013.01);
Abstract

An integrated circuit (IC) includes a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer. A logic device includes a logic gate arranged over the semiconductor device layer. The logic gate is arranged within a high κ dielectric layer. A memory cell includes a control gate and a select gate laterally adjacent to one another and arranged over the semiconductor device layer. A charge-trapping layer underlies the control gate.

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