The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2023

Filed:

Nov. 23, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Vehid Suljic, Meridian, ID (US);

Matthew D. Rowley, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02J 7/34 (2006.01); H02J 9/06 (2006.01); H02J 7/18 (2006.01); G06F 3/06 (2006.01); G06F 13/28 (2006.01); G01R 27/28 (2006.01); G01R 31/14 (2006.01); H01M 10/52 (2006.01); H01M 10/46 (2006.01); H01M 10/48 (2006.01); H02J 7/00 (2006.01);
U.S. Cl.
CPC ...
H02J 7/345 (2013.01); G06F 3/0625 (2013.01); H02J 7/0018 (2013.01); H02J 9/061 (2013.01); G01R 27/28 (2013.01); G01R 31/14 (2013.01); G06F 13/28 (2013.01); H01M 10/46 (2013.01); H01M 10/48 (2013.01); H01M 10/52 (2013.01);
Abstract

Various embodiments described herein use a set of capacitor sets (e.g., capacitor banks) in a power backup architecture for a memory sub-system, where each capacitor set can be individually checked for a health condition (e.g., in parallel) to determine their respective health after the memory sub-system has completed a boot process. In response to determining that at least one capacitor set has failed the health condition (or a certain number of capacitor sets have failed the health condition), the memory sub-system can perform certain operations prior to primary power loss to the memory sub-system (e.g., preemptively performs a data backup process to ensure data integrity) and can adjust the operational mode of the memory sub-system (e.g., switch it from read-write mode to read-only mode).


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