The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2023

Filed:

Sep. 28, 2021
Applicant:

Parade Technologies, Ltd., San Jose, CA (US);

Inventors:

Yueh-Lin Yang, Zhubei, TW;

Haijun Chen, Shanghai, CN;

Tatao Hsu, Taipei, TW;

Jonathan Huang, Taipei, TW;

Assignee:

PARADE TECHNOLOGIES, LTD., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); G02F 1/1345 (2006.01);
U.S. Cl.
CPC ...
H01L 27/124 (2013.01); G02F 1/13452 (2013.01); G02F 1/13456 (2021.01); G02F 1/13458 (2013.01);
Abstract

An electronic device has a display substrate including a display area, a driver area, and a fan-out area. The fan-out area has interconnects providing electrical accesses to display elements of the display area. The device has a driver chip disposed on the driver area. The driver chip includes a first edge adjacent to the display area and multiple pad groups, each pad group including a respective row of electronic pads that is (i) arranged substantially in parallel with the first edge and (ii) electrically coupled to a respective subset of display elements via respective interconnects routed on a respective region of the fan-out area. The pad groups include a first pad group and a second pad group. The first and second pad groups have two different distances from the first edge and correspond to two different subsets of interconnects routed on two non-overlapping regions of the fan-out area.


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