Sense timing coordination for memory

Abstract

Methods, systems, and devices for sense timing coordination are described. In some systems, to sense the logic states of memory cells, a memory device may generate an activation signal and route the activation signal over a signal line (e.g., a dummy word line) located at a memory array level of the memory device to one or more sense amplifiers. Based on receiving the activation signal, a sense amplifier may latch and determine the logic state of a corresponding memory cell. A first sense amplifier may sense a state of a first memory cell at a first time and a second sense amplifier may sense a state of a second memory cell at a second time in response to the same activation signal due to a propagation delay of the activation signal routed over the signal line (e.g., and corresponding to a propagation delay for activating a word line).