The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2023

Filed:

Dec. 06, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

John E. Maroney, Irvine, CA (US);

Christopher J. Bueb, Folsom, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06F 13/16 (2006.01); G06F 12/10 (2016.01); G06F 9/455 (2018.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4027 (2013.01); G06F 9/455 (2013.01); G06F 12/10 (2013.01); G06F 13/1668 (2013.01); G06F 13/4282 (2013.01); G06F 2212/657 (2013.01); G06F 2213/0026 (2013.01);
Abstract

A processing device to perform operations including detecting a first host system connected to a first interface port of a plurality of interface ports of a memory device, detecting a second host system connected to a second interface port of the plurality of interface ports, allocating a first range of logical block addresses (LBA) to one or more virtual functions (VFs) assigned to the first host system, and allocating a second range of LBAs to one or more VFs assigned to the second host system, wherein the first host system is to access the first range of LBA of the memory device concurrently with the second host system accessing the second range of LBA of the memory device, and wherein the first range of LBAs is different than the second range of LBAs.


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