The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2023

Filed:

Aug. 24, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Szu-Lin Liu, Hsinchu, TW;

Jaw-Juinn Horng, Hsinchu, TW;

Yi-Hsiang Wang, Hsinchu, TW;

Wei-Lin Lai, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/12 (2006.01); H03K 5/1252 (2006.01); H03K 19/0185 (2006.01); H01L 21/8234 (2006.01); H01L 27/06 (2006.01); H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
H03K 5/1252 (2013.01); H01L 21/823437 (2013.01); H01L 21/823475 (2013.01); H01L 27/0629 (2013.01); H01L 29/94 (2013.01); H03K 19/018521 (2013.01);
Abstract

An integrated circuit includes a first metal-insulator-semiconductor capacitor, a second metal-insulator-semiconductor capacitor, and a metal-insulator-metal capacitor. A first terminal of the first metal-insulator-semiconductor capacitor is configured to receive a first reference voltage for a higher voltage domain, while a first terminal of the second metal-insulator-semiconductor capacitor is configured to receive a second reference voltage for the higher voltage domain. A second terminal of the first metal-insulator-semiconductor capacitor is conductively connected to a first terminal of the metal-insulator-metal capacitor, while a second terminal of the second metal-insulator-semiconductor capacitor is conductively connected to a second terminal of the metal-insulator-metal capacitor. The first terminal of the metal-insulator-metal capacitor is configured to receive a first supply voltage for a lower voltage domain, and the first terminal of the second metal-insulator-semiconductor capacitor is configured to receive a second supply voltage for the lower voltage domain.


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