The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2023

Filed:

May. 19, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yun-Yan Chung, Hsinchu, TW;

Chao-Ching Cheng, Hsinchu, TW;

Chao-Hsin Chien, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 29/68 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 29/76 (2006.01); H01L 29/24 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78645 (2013.01); H01L 21/0262 (2013.01); H01L 21/02565 (2013.01); H01L 21/02568 (2013.01); H01L 29/24 (2013.01); H01L 29/42384 (2013.01); H01L 29/66969 (2013.01); H01L 29/685 (2013.01); H01L 29/7606 (2013.01); H01L 29/7869 (2013.01); H01L 29/78648 (2013.01); H01L 29/78696 (2013.01);
Abstract

In an embodiment, a method includes forming a first gate electrode over a substrate. The method also includes forming a first gate dielectric layer over the first gate electrode. The method also includes depositing a semiconductor layer over the first gate dielectric layer. The method also includes forming source/drain regions over the first gate dielectric layer and the semiconductor layer, the source/drain regions overlapping ends of the semiconductor layer. The method also includes forming a second gate dielectric layer over the semiconductor layer and the source/drain regions. The method also includes and forming a second gate electrode over the second gate dielectric layer.


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