The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2023

Filed:

Jun. 22, 2020
Applicant:

Hitachi High-tech Corporation, Tokyo, JP;

Inventors:

Naoaki Kondo, Tokyo, JP;

Minoru Harada, Tokyo, JP;

Yohei Minekawa, Tokyo, JP;

Takehiro Hirai, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/67 (2006.01); G06T 7/00 (2017.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67253 (2013.01); G06T 7/001 (2013.01); H01L 22/26 (2013.01); G06T 2207/10061 (2013.01); G06T 2207/30148 (2013.01);
Abstract

Provided is a wafer observation apparatus includes: a scanning electron microscope; a control unit which includes a wafer observation unit that observes a wafer of a semiconductor device, and an image acquisition unit that acquires a wafer image; a storage unit which includes an image storage unit that stores the wafer image and a template image, and a recipe storage unit that stores a wafer alignment recipe including a matching success and failure determination threshold value, an image processing parameter set, and a use priority associated with the template image; and a calculation unit which includes a recipe reading unit that reads the template image and the wafer alignment recipe, a recipe update necessity determination unit that determines update necessity of the wafer alignment recipe, and a recipe updating unit that updates the wafer alignment recipe based on a determination result in the recipe update necessity determination unit.


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