The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 06, 2023
Filed:
May. 07, 2019
Intel Corporation, Santa Clara, CA (US);
Vedaraman Geetha, Fremont, CA (US);
Jeffrey Baxter, Cupertino, CA (US);
Sai Prashanth Muralidhara, Portland, OR (US);
Sharada Venkateswaran, San Francisco, CA (US);
Daniel Liu, Walnut Creek, CA (US);
Nishant Singh, Bengaluru, IN;
Bahaa Fahim, Santa Clara, CA (US);
Samuel D. Strom, Folsom, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A processor includes one or more cores having cache, a cache home agent (CHA), a near memory controller, to near memory, and a far memory controller, which is to: receive a first memory read operation from the CHA directed at a memory address; detect a miss for the first memory address at the near memory; issue a second memory read operation to the far memory controller to retrieve a cache line, having first data, from the memory address of far memory; receive the cache line from the far memory controller in response to the second memory read operation; and send the cache line to the CHA with a forced change to a directory state of the cache line at the CHA, the forced change to cause the CHA to snoop remote sockets to maintain data coherence for the cache line in an absence of directory state in the far memory.