The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2023

Filed:

Aug. 30, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Prashant D. Chaudhari, Folsom, CA (US);

Bradley T. Coffman, Hillsboro, OR (US);

Gustavo P. Espinosa, Portland, OR (US);

Ivan Rodrigo Herrera Mejia, El Dorado Hills, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06F 11/30 (2006.01); G06F 1/30 (2006.01); G05F 1/56 (2006.01); G05F 1/575 (2006.01);
U.S. Cl.
CPC ...
G06F 11/0793 (2013.01); G05F 1/562 (2013.01); G05F 1/575 (2013.01); G06F 1/30 (2013.01); G06F 11/3058 (2013.01);
Abstract

Methods, systems and apparatuses may provide for technology that includes a system on chip (SoC) having an integrated voltage regulator and a power management controller, and a first communication path coupled to the power management controller, wherein the first communication path is to carry power error information to the power management controller. The technology may also include a second communication path coupled to an error pin of the SoC, wherein the second communication path is to carry the power error information to the error pin, and wherein the power error information is associated with the integrated voltage regulator.


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