Vertical memory devices with high density dummy channel structure

Abstract

Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a substrate, a plurality of gate layers, and a plurality of insulating layers. The plurality of gate layers and the plurality of insulating layers are stacked alternately over a first region of the substrate and are stacked of a stair-step form over a second region of the substrate. The semiconductor device also includes a channel structure that is disposed over the first region and through the plurality of gate layers and the plurality of insulating layers. The channel structure and the plurality of gate layers form a stack of transistors in a series configuration with the plurality of gate layers being a plurality of gates for the stack of transistors. The semiconductor device also includes a first dummy channel structure that is disposed through a first stair region of the stair-step form, a second dummy channel structure that is disposed through a second stair region of the stair-step form adjacent to the first stair region, and a third dummy channel structure that is disposed at a boundary between the first stair region and the second stair region.