The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 30, 2023
Filed:
Feb. 10, 2021
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/267 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 29/778 (2006.01); H01L 21/762 (2006.01); H01L 21/8252 (2006.01); H01L 29/06 (2006.01); H01L 29/205 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7851 (2013.01); H01L 21/0259 (2013.01); H01L 21/02636 (2013.01); H01L 21/02639 (2013.01); H01L 21/02658 (2013.01); H01L 21/76224 (2013.01); H01L 21/8252 (2013.01); H01L 29/0649 (2013.01); H01L 29/1037 (2013.01); H01L 29/1054 (2013.01); H01L 29/205 (2013.01); H01L 29/267 (2013.01); H01L 29/66462 (2013.01); H01L 29/66522 (2013.01); H01L 29/66795 (2013.01); H01L 29/7786 (2013.01); H01L 29/785 (2013.01); H01L 29/7842 (2013.01); H01L 29/7848 (2013.01);
Abstract
A field effect transistor (FET) device includes a substrate, a gate structure over the substrate, a channel region under the gate structure, the channel region including a first semiconductor material, and a second semiconductor material interposed between the first semiconductor material and the substrate. The second semiconductor material is different from the first semiconductor material. An interface of the second semiconductor material with the first semiconductor material has facets. A surface of the second semiconductor material interfacing with the substrate is non-planar.