The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2023

Filed:

Jul. 05, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Hartmut Penner, San Jose, CA (US);

Dharmendra S. Modha, San Jose, CA (US);

John V. Arthur, Mountain View, CA (US);

Andrew S. Cassidy, San Jose, CA (US);

Rathinakumar Appuswamy, San Jose, CA (US);

Pallab Datta, San Jose, CA (US);

Steven K. Esser, San Jose, CA (US);

Myron D. Flickner, San Jose, CA (US);

Jennifer Klamo, San Jose, CA (US);

Jun Sawada, Austin, TX (US);

Brian Taba, Cupertino, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/08 (2023.01); G06N 5/046 (2023.01); G06N 3/045 (2023.01);
U.S. Cl.
CPC ...
G06N 3/08 (2013.01); G06N 3/045 (2023.01); G06N 5/046 (2013.01);
Abstract

Instruction distribution in an array of neural network cores is provided. In various embodiments, a neural inference chip is initialized with core microcode. The chip comprises a plurality of neural cores. The core microcode is executable by the neural cores to execute a tensor operation of a neural network. The core microcode is distributed to the plurality of neural cores via an on-chip network. The core microcode is executed synchronously by the plurality of neural cores to compute a neural network layer.


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