The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2023

Filed:

Jul. 12, 2021
Applicant:

Weebit Nano Ltd., Hod Hasharon, IL;

Inventor:

Lior Dagan, Tzafon, IL;

Assignee:

WEEBIT NANO LTD., Hod Hasharon, IL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); H01L 27/24 (2006.01); H01L 27/12 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2436 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); H01L 27/1203 (2013.01); G11C 2213/74 (2013.01); G11C 2213/79 (2013.01);
Abstract

A resistive random-access memory (ReRAM) array is provided. The ReRAM array includes a silicon over insulator (SOI) substrate; a first bit line; a first inverted bit line of the first bit line; a second bit line; a second inverted bit line of the second bit line; a first word line; a first inverted word line of the first word line; a first ReRAM cell comprising a first MOSFET, a second MOSFET, and a resistive element; and a second ReRAM cell comprising a first MOSFET, a second MOSFET, and a resistive element connected in series; wherein upon applying a predefined potential on elements of the first ReRAM cell, a state of the first ReRAM cell is adjusted without effecting a state of the second ReRAM.


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