Leakage current reduction in electronic devices

Abstract

Methods, systems, and devices for leakage current reduction in electronic devices are described. Electronic devices may be susceptible to leakage currents when operating in a first mode, such as an inactive (e.g., a standby) mode. To mitigate leakage current, an electronic device may include transistors coupled in cascode configuration where a gate of a drain-side transistor in the cascode configuration is configured to be biased by an adjustable (e.g., a dynamic) control signal. When the transistors are inactive (e.g., 'off'), the control signal may be adjusted to prevent leakage associated with the inactive transistors. Further, a source-side transistor in the cascode configuration may be configured to have a high threshold voltage (e.g., relative to the drain-side transistor).