The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2023

Filed:

Nov. 03, 2020
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventor:

Bed Raj Kandel, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/94 (2006.01); H01L 23/528 (2006.01); H01L 27/10 (2006.01); H01L 27/105 (2023.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/94 (2013.01); H01L 23/528 (2013.01); H01L 27/101 (2013.01); H01L 27/105 (2013.01); H01L 29/0696 (2013.01);
Abstract

High-density metal-oxide semiconductor (MOS) capacitor (MOSCAP) cell circuits and MOS device array circuits are disclosed. A gate comprising a selected aspect ratio disposed in a MOSCAP cell circuit comprising a cell region is configured to increase a capacitive density by increasing an extent to which metal routing layers contribute to a total MOSCAP cell circuit capacitance. An area of a MOSCAP array circuit is also reduced. Also, bulk tie cells are disposed within a MOS device array circuit in array diffusion regions to increased MOS device array circuit density. The array diffusion regions include a first device region including MOS devices and a bulk tie region including the bulk tie cells. The bulk tie region is isolated from the first device region by a diffusion cut. A diffusion cut is between a first gate on the device region and a second gate on the bulk tie region.


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