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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11658228 B1

PDFFull Text
Date of Patent:
May. 23, 2023

Filed:

Jun. 09, 2021

Semiconductor device layout structure manufacturing method

Applicants:

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

Gang Qian, Shanghai, CN;

Yiming Miao, Shanghai, CN;

Yanlin Sun, Shanghai, CN;

Xubo Chen, Shanghai, CN;

Assignees:

SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, Beijing, CN;

SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, Shanghai, CN;

Attorney:

Anova Law Group, PLLC

Primary Examiner:

Joseph C Nicely

Assistant Examiner:

Lamont B Koo

Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); G11C 11/417 (2006.01); H01L 21/265 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 23/535 (2006.01); H01L 27/11 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); G11C 11/417 (2013.01); H01L 21/265 (2013.01); H01L 21/76224 (2013.01); H01L 21/76895 (2013.01); H01L 21/823475 (2013.01); H01L 23/535 (2013.01); H01L 27/1104 (2013.01); H01L 27/1112 (2013.01); H01L 29/0649 (2013.01); H01L 29/78 (2013.01);
Abstract

A method for manufacturing semiconductor devices is provided. The method includes: providing a substrate structure comprising a semiconductor substrate and a trench insulator portion in the semiconductor substrate; forming a dummy gate on the semiconductor substrate; performing a first ion implantation into the semiconductor substrate to form a first doped region between the trench insulator portion and the dummy gate; and forming a first connecting member connecting the dummy gate with the first doped region.

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Qian, Gang. (2023). Semiconductor device layout structure manufacturing method (U.S. Patent No. 11658228). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11658228

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